hsk_boot.c File Reference

HSK Boot implementation. More...

#include <Infineon/XC878.h>
#include "hsk_boot.h"
#include "../hsk_isr/hsk_isr.h"
#include "../hsk_io/hsk_io.h"

Include dependency graph for hsk_boot.c:

Macros
#define	BIT_MXB   0
	MEX3 XRAM Bank Number bits. More...
#define	CNT_MXB   3
	MEX3 XRAM Bank Number bit count. More...
#define	BIT_MXB19   4
	MEX3 XRAM Bank Number highest bit. More...
#define	XRAM_BANK   0xF
	The selected XRAM bank number. More...
#define	BIT_MXM   3
	MEX3 XRAM Bank Selector bit. More...
#define	XRAM_SELECTOR   1
	Set BIT_MXM to access the data memroy bank with MOVX instructions. More...
#define	PDATA_PAGE   0xF0
	The page to locate pdata at. More...
#define	BIT_EXTOSCR   0
	OSC_CON bit. More...
#define	BIT_EORDRES   1
	OSC_CON bit. More...
#define	BIT_OSCSS   2
	OSC_CON bit. More...
#define	BIT_XPD   3
	OSC_CON bit. More...
#define	BIT_PLLPD   5
	OSC_CON bit. More...
#define	BIT_PLLBYP   6
	OSC_CON bit. More...
#define	BIT_PLLRDRES   7
	OSC_CON bit. More...
#define	BIT_PLL_LOCK   0
	PLL_CON bit. More...
#define	BIT_PLLR   1
	PLL_CON bit. More...
#define	BIT_PDIV   0
	PLL_CON1 bit. More...
#define	CNT_PDIV   5
	PDIV bit count. More...
#define	BIT_NDIVL   2
	PLL_CON low PLL NF-Divider bits. More...
#define	CNT_NDIVL   6
	NDIVL bit count. More...
#define	BIT_NDIVH   5
	PLL_CON1 high PLL NF-Divider bits. More...
#define	CNT_NDIVH   3
	NDIVH bit count. More...
#define	BIT_NMIPLL   1
	NMICON PLL Loss of Clock NMI Enable bit. More...

Functions
void	hsk_boot_io (void)
	Initialises all IO ports as input ports without pull. More...
void	hsk_boot_mem (void)
	Sets up xdata and pdata memory access. More...
ubyte	_sdcc_external_startup (void)
	Turns off pullup/-down for all ports prior to global/static initialisation. More...
void	hsk_boot_isr_nmipll (void)
	Loss of clock recovery ISR. More...
void	hsk_boot_extClock (const ulong clk)
	Switches to an external oscilator. More...

Variables
struct {
ubyte   pdiv
	The PDIV value for the configured clock speed. More...
uword   ndiv
	The NDIV value for the configured clock speed. More...
}	boot
	Boot parameter storage for the loss of clock ISR callback. More...

Detailed Description

HSK Boot implementation.

The High Speed Karlsruhe XC878 boot up code implementation.

This obsoletes 3rd party provided assembler boot code.

Author

kami

Macro Definition Documentation

BIT_EORDRES

#define BIT_EORDRES   1

OSC_CON bit.

External Oscillator Watchdog Reset, used when switching to an external clock.

BIT_EXTOSCR

#define BIT_EXTOSCR   0

OSC_CON bit.

External Oscillator Run Status Bit, used to determine whether the external oscilator is available.

BIT_MXB

#define BIT_MXB   0

MEX3 XRAM Bank Number bits.

Used to select the memory bank where the XRAM is located. This 4 bit field is divided, the highest bit goes into the BIT_MXB19 bit.

BIT_MXB19

#define BIT_MXB19   4

MEX3 XRAM Bank Number highest bit.

The final MXB bit.

BIT_MXM

#define BIT_MXM   3

MEX3 XRAM Bank Selector bit.

BIT_NDIVH

#define BIT_NDIVH   5

PLL_CON1 high PLL NF-Divider bits.

BIT_NDIVL

#define BIT_NDIVL   2

PLL_CON low PLL NF-Divider bits.

BIT_NMIPLL

#define BIT_NMIPLL   1

NMICON PLL Loss of Clock NMI Enable bit.

BIT_OSCSS

#define BIT_OSCSS   2

OSC_CON bit.

Oscillator Source Select, used to turn the external oscillator on(1)/off(0).

BIT_PDIV

#define BIT_PDIV   0

PLL_CON1 bit.

Something to do with the CPU clock.

BIT_PLL_LOCK

#define BIT_PLL_LOCK   0

PLL_CON bit.

PLL Lock Status Flag, used when switching to an external clock.

BIT_PLLBYP

#define BIT_PLLBYP   6

OSC_CON bit.

PLL Output Bypass Control, used when switching to an external clock.

BIT_PLLPD

#define BIT_PLLPD   5

OSC_CON bit.

PLL Power Down Control, used when switching to an external clock.

BIT_PLLR

#define BIT_PLLR   1

PLL_CON bit.

PLL Run Status Flag, used when switching to an external clock.

BIT_PLLRDRES

#define BIT_PLLRDRES   7

OSC_CON bit.

PLL Watchdog Reset, used when switching to an external clock.

BIT_XPD

#define BIT_XPD   3

OSC_CON bit.

XTAL Power Down Control, used when switching to an external clock.

CNT_MXB

#define CNT_MXB   3

MEX3 XRAM Bank Number bit count.

CNT_NDIVH

#define CNT_NDIVH   3

NDIVH bit count.

CNT_NDIVL

#define CNT_NDIVL   6

NDIVL bit count.

CNT_PDIV

#define CNT_PDIV   5

PDIV bit count.

PDATA_PAGE

#define PDATA_PAGE   0xF0

The page to locate pdata at.

Use the first XRAM page, because that is where the compilers expect it.

XRAM_BANK

#define XRAM_BANK   0xF

The selected XRAM bank number.

XRAM_SELECTOR

#define XRAM_SELECTOR   1

Set BIT_MXM to access the data memroy bank with MOVX instructions.

Otherwise the current bank (whichever that is) would be addressed. MOVX is used to access external memory. The data memory bank is selected with the MXB bits.

Function Documentation

_sdcc_external_startup()

ubyte _sdcc_external_startup ( void  )

private

Turns off pullup/-down for all ports prior to global/static initialisation.

This function is automatically linked by SDCC and called from startup.a51 by Keil C51.

Returns

Always returns 0, which indicates that SDCC should initialise globals and statics

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hsk_boot_extClock()

void hsk_boot_extClock

(

const ulong

clk

)

Switches to an external oscilator.

This function requires xdata access.

The implemented process is named: "Select the External Oscillator as PLL input source"

The following is described in more detail in chapter 7.3 of the XC878 User Manual.

The XC878 can either use an internal 4MHz oscilator (default) or an external oscilator from 2 to 20MHz, normally referred to as FOSC. A phase-locked loop (PLL) converts it to a faster internal speed FSYS, 144MHz by default.

This implementation is currently limited to oscilators from 2MHz to 20MHz in 1MHz intervals.

The oscilator frequency is vital for external communication (e.g. CAN) and timer/counter speeds.

This implementation switches to an external clock ensuring that the PLL generates a 144MHz FSYS clock. The CLKREL divisor set to 6 generates the fast clock (FCLK) that runs at 48MHz. The remaining clocks, i.e. peripheral (PCLK), CPU (SCLK, CCLK), have a fixed divisor by 2, so they run at 24MHz.

After setting up the PLL, this function will register an ISR, that will attempt to reactivate the external oscillator in a PLL loss-of-clock event.

Parameters

clk	The frequency of the external oscilator in Hz.

WARNING - Here be dragons ...

Before messing with this stuff you should be aware that this is tricky business. Mistakes can result in hardware damage. Or at least all your timers and external interfaces will act weird.

Basically this bypasses/turns off the PLL, sets up the external oscilator and than reconfigures the PLL and brings it back into play.

Many of the OSC_CON, which is on page 1, bits are write protected. The MAIN_vUnlockProtecReg() turns the protection off for 32 cycles. So it has to be turned off each time protected bits are accessed.

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hsk_boot_io()

void hsk_boot_io ( void  )

private

Initialises all IO ports as input ports without pull.

hsk_boot_isr_nmipll()

void hsk_boot_isr_nmipll ( void  )

private

Loss of clock recovery ISR.

This takes very long.

hsk_boot_mem()

void hsk_boot_mem ( void  )

private

Sets up xdata and pdata memory access.

Refer to the Processor Architecture and Memory Organization chapters of the XC878 User Manual.

Variable Documentation

boot

boot

static

Boot parameter storage for the loss of clock ISR callback.

ndiv

uword ndiv

The NDIV value for the configured clock speed.

See table 7-5 in the data sheet for desired NDIV values. See the NDIV description for value encoding.

pdiv

ubyte pdiv

The PDIV value for the configured clock speed.

See table 7-5 in the data sheet for desired PDIV values. See the PDIV description for value encoding.