hsk-libs-dev  270
High Speed Karlsruhe XC878 library collection
hsk_boot.h
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1 /** \file
2  * HSK Boot headers
3  *
4  * This file contains the prototypes to put the µC into working condition.
5  *
6  * Currently implemented:
7  * - hsk_boot_extClock()
8  * Activates external clock input and sets up the PLL, this
9  * is important when communicating with other devices, the
10  * internal clock is not sufficiently precise
11  *
12  * Linking this library also automatically causes the following boot actions:
13  * - Deactivate all internal pullup devices
14  * - Activate XDATA access
15  * - Set the PDATA page to the first XDATA block
16  *
17  * @author kami
18  */
19 
20 #ifndef _HSK_BOOT_H_
21 #define _HSK_BOOT_H_
22 
23 /*
24  * Required for SDCC to propagate ISR prototypes.
25  */
26 #ifdef SDCC
27 #include "../hsk_isr/hsk_isr.isr"
28 #endif /* SDCC */
29 
30 /**
31  * Switches to an external oscilator.
32  *
33  * This function requires xdata access.
34  *
35  * The implemented process is named:
36  * "Select the External Oscillator as PLL input source"
37  *
38  * The following is described in more detail in chapter 7.3 of the XC878
39  * User Manual.
40  *
41  * The XC878 can either use an internal 4MHz oscilator (default) or an
42  * external oscilator from 2 to 20MHz, normally referred to as FOSC.
43  * A phase-locked loop (PLL) converts it to a faster internal speed FSYS,
44  * 144MHz by default.
45  *
46  * This implementation is currently limited to oscilators from 2MHz to 20MHz
47  * in 1MHz intervals.
48  *
49  * The oscilator frequency is vital for external communication (e.g. CAN)
50  * and timer/counter speeds.
51  *
52  * This implementation switches to an external clock ensuring that the
53  * PLL generates a 144MHz FSYS clock. The CLKREL divisor set to 6 generates
54  * the fast clock (FCLK) that runs at 48MHz. The remaining clocks, i.e.
55  * peripheral (PCLK), CPU (SCLK, CCLK), have a fixed divisor by 2, so
56  * they run at 24MHz.
57  *
58  * After setting up the PLL, this function will register an ISR, that will
59  * attempt to reactivate the external oscillator in a PLL loss-of-clock
60  * event.
61  *
62  * @param clk
63  * The frequency of the external oscilator in Hz.
64  */
65 void hsk_boot_extClock(const ulong clk);
66 
67 #endif /* _HSK_BOOT_H_ */
void hsk_boot_extClock(const ulong clk)
Switches to an external oscilator.
Definition: hsk_boot.c:323