hsk_pwm.c File Reference

HSK Pulse Width Modulation implementation. More...

#include <Infineon/XC878.h>
#include "hsk_pwm.h"

Include dependency graph for hsk_pwm.c:

Macros
#define	BIT_CCUCCFG   5
	CR_MISC CCU6 Clock Configuration bit. More...
#define	BIT_TnCLK   0
	CCU6_TCTR0L/CCU6_TCTR0H Timer T12/T13 Input Clock Select and Prescaler bits. More...
#define	CNT_TnCLK   4
	TnCLK bit count. More...
#define	BIT_PSL   0
	PSLR Compare Outputs Passive State Level bits. More...
#define	CNT_PSL   6
	PSL bit count. More...
#define	BIT_PSL63   7
	PSLR Passive State Level of Output COUT63 bit. More...
#define	BIT_TnMODEN   0
	CCU6_MODCTRL/CCU6_MODCTRH T12/T13 Modulation Enable bits. More...
#define	CNT_TnMODEN   6
	TnMODEN bit count. More...
#define	BIT_ECT13O   7
	CCU6_MODCTRH Enable Compare Timer T13 Output bits. More...
#define	CNT_MSEL6n   4
	T12MSELL/H Capture/Compare Mode Selection width. More...
#define	MOD_MSEL6n   0x3
	T12MSELL/H Capture/Compare Mode Selection mode. More...
#define	BIT_TnSTR   6
	CCU6_TCTR4L/CCU6_TCTR4H Timer T12/T13 Shadow Transfer Request bit. More...
#define	BIT_CCU_DIS   2
	PMCON1 Capture Compare Unit Disable bit. More...
#define	BIT_TnRR   0
	CCU6_TCTR4L/CCU6_TCTR4H Timer T12/T13 Run Reset bit. More...
#define	BIT_TnRS   1
	CCU6_TCTR4L/CCU6_TCTR4H Timer T12/T13 Run Set bit. More...

Functions
void	hsk_pwm_init (const hsk_pwm_channel channel, const ulong freq)
	Sets up the the CCU6 timer frequencies that control the PWM cycle. More...
void	hsk_pwm_port_open (const hsk_pwm_port port)
	Set up a PWM output port. More...
void	hsk_pwm_port_close (const hsk_pwm_port port)
	Close a PWM output port. More...
void	hsk_pwm_channel_set (const hsk_pwm_channel channel, const uword max, const uword value)
	Set the duty cycle for the given channel. More...
void	hsk_pwm_outChannel_dir (hsk_pwm_outChannel channel, const bool up)
	Set the direction of an output channel. More...
void	hsk_pwm_enable (void)
	Turns on the CCU6. More...
void	hsk_pwm_disable (void)
	Deactivates the CCU6 to reduce power consumption. More...

Variables
struct {
ubyte   pos
	The Pn_ALTSEL[01] bit position to make the port configuration in. More...
ubyte   sel
	Select a 2 bits Pn_ALTSEL[01] configuration. More...
}	ports []
	Data structure to hold output port configurations. More...

Detailed Description

HSK Pulse Width Modulation implementation.

This would mostly be straightforward if it wasn't for the messy output channel configuration.

The init function buys a lot of simplicity by limiting the CCU6 use to generating PWM. Also, the channels PWM_60, PWM_61 and PWM_62 operate at the same base frequency and period. This is a hardware limitation.

Author

kami

Macro Definition Documentation

BIT_CCU_DIS

#define BIT_CCU_DIS   2

PMCON1 Capture Compare Unit Disable bit.

BIT_CCUCCFG

#define BIT_CCUCCFG   5

CR_MISC CCU6 Clock Configuration bit.

BIT_ECT13O

#define BIT_ECT13O   7

CCU6_MODCTRH Enable Compare Timer T13 Output bits.

BIT_PSL

#define BIT_PSL   0

PSLR Compare Outputs Passive State Level bits.

BIT_PSL63

#define BIT_PSL63   7

PSLR Passive State Level of Output COUT63 bit.

BIT_TnCLK

#define BIT_TnCLK   0

CCU6_TCTR0L/CCU6_TCTR0H Timer T12/T13 Input Clock Select and Prescaler bits.

BIT_TnMODEN

#define BIT_TnMODEN   0

CCU6_MODCTRL/CCU6_MODCTRH T12/T13 Modulation Enable bits.

BIT_TnRR

#define BIT_TnRR   0

CCU6_TCTR4L/CCU6_TCTR4H Timer T12/T13 Run Reset bit.

BIT_TnRS

#define BIT_TnRS   1

CCU6_TCTR4L/CCU6_TCTR4H Timer T12/T13 Run Set bit.

BIT_TnSTR

#define BIT_TnSTR   6

CCU6_TCTR4L/CCU6_TCTR4H Timer T12/T13 Shadow Transfer Request bit.

CNT_MSEL6n

#define CNT_MSEL6n   4

T12MSELL/H Capture/Compare Mode Selection width.

CNT_PSL

#define CNT_PSL   6

PSL bit count.

CNT_TnCLK

#define CNT_TnCLK   4

TnCLK bit count.

CNT_TnMODEN

#define CNT_TnMODEN   6

TnMODEN bit count.

MOD_MSEL6n

#define MOD_MSEL6n   0x3

T12MSELL/H Capture/Compare Mode Selection mode.

This mode means CC6n and COUT6n are in output mode.

Function Documentation

hsk_pwm_channel_set()

void hsk_pwm_channel_set	(	const hsk_pwm_channel	channel,
		const uword	max,
		const uword	value
	)

Set the duty cycle for the given channel.

I.e. the active time frame slice of period can be set with max and value.

To set the duty cycle in percent specify a max of 100 and values from 0 to 100.

Parameters

channel	The PWM channel to set the duty cycle for, check the PWM_6x defines
max	Defines the scope value can move in
value	The current duty cycle value

hsk_pwm_disable()

void hsk_pwm_disable

(

void

)

Deactivates the CCU6 to reduce power consumption.

hsk_pwm_enable()

void hsk_pwm_enable

(

void

)

Turns on the CCU6.

Deactivates the power disable mode and sets the T12 and T13 Timer Run bits.

Precondition

All hsk_pwm_init() calls have to be completed to call this

hsk_pwm_init()

void hsk_pwm_init	(	const hsk_pwm_channel	channel,
		const ulong	freq
	)

Sets up the the CCU6 timer frequencies that control the PWM cycle.

The channels PWM_60, PWM_61 and PWM_62 share the timer T12, thus initializing one of them, initializes them all. The channel PWM_63 has exclusive use of the timer T13 and can thus be used with its own operating frequency.

Frequencies up to ~732.4Hz are always between 15 and 16 bits precision.

Frequencies above 48kHz offer less than 1/1000 precision. From there it is a linear function, i.e. 480kHz still offer 1/100 precision.

The freq value 0 will result in ~0.02Hz ( ).

The following formula results in the freq value that yields exactly the desired precision, this is useful to avoid precision loss by rounding:

E.g. 10 bit precision:

Parameters

channel	The channel to change the frequency for
freq	The desired PWM cycle frequency in units of 0.1Hz

PWM Timings

The CCU6CLK can run at FCLK (48MHz) or PCLK (24MHz), configured in the CCUCCFG bit. This implementation always uses 48MHz.

The T12CLK can run any power of two between CCU6CLK and CCU6CLK/128, configured in the T12CLK bit field.

This value can additionally be multiplied with a prescaler of 1/256, activated with the T12PRE bit.

The same is true for the T13CLK.

Additionally the period is length for T12 and T13 can be configured to any 16 bit value. Assuming at least 1/1000 precision is desired that means the clock cycle can be shortened by any factor up to 2^6 (64).

The conclusion is that PWM frequencies between 48kHz and ~0.02Hz can be configured. Very high values degrade the precision, e.g. 96kHz will only offer 1/500 precision. The freq value 0 will result in ~0.02Hz ( ).

hsk_pwm_outChannel_dir()

void hsk_pwm_outChannel_dir	(	hsk_pwm_outChannel	channel,
		const bool	up
	)

Set the direction of an output channel.

The channel value can be taken from any of the PWM_CCx/PWM_COUTx defines.

Parameters

channel	The IO channel to set the direction bit for
up	Set 1 to output a 1 during the cycle set with hsk_pwm_channel_set(), set 0 to output a 0 during the cycle set with hsk_pwm_channel_set()

hsk_pwm_port_close()

void hsk_pwm_port_close

(

const hsk_pwm_port

port

)

Close a PWM output port.

This configures the necessary port direction bits.

The port can be any one of the PWM_OUT_x_* defines.

Parameters

port	The output port to deactivate

hsk_pwm_port_open()

void hsk_pwm_port_open

(

const hsk_pwm_port

port

)

Set up a PWM output port.

This configures the necessary port direction bits and activates the corresponding output channels.

The port can be any one of the PWM_OUT_x_* defines.

Precondition

This function should only be called after hsk_pwm_enable(), otherwise the output port will be driven (1) until PWM is enabled

Parameters

port	The output port to activate

Variable Documentation

ports

ports

static

Initial value:

= {
         {0, 1},
         {1, 1},
         {0, 1},
         {1, 1},
         {0, 2},
         {1, 2},
         {1, 2},
         {2, 1},
         {3, 1},
         {4, 1},
         {5, 1},
         {4, 2},
         {5, 2},
         {4, 1},
         {5, 1},
         {6, 1},
         {7, 1},
         {3, 2},
         {7, 1},
         {3, 2}
}

Data structure to hold output port configurations.

pos

ubyte pos

The Pn_ALTSEL[01] bit position to make the port configuration in.

sel

ubyte sel

Select a 2 bits Pn_ALTSEL[01] configuration.